1. Field of the Invention
The present invention relates to semiconductor device assemblies, or so-called “multi-chip modules,” in which two or more semiconductor devices are stacked relative to one another. More specifically, the present invention relates to semiconductor device assemblies in which the distances between adjacent stacked semiconductor devices are determined, at least in part, by the heights of structures protruding from bond pads on an active surface of the lower of the adjacent stacked semiconductor devices.
2. Background of Related Art
In order to conserve the amount of surface area, or “real estate,” consumed on a carrier substrate, such as a circuit board, by semiconductor devices connected thereto, various types of increased density packages have been developed. Among these semiconductor device packages are the so-called multi-chip module (MCM), which includes assemblies of semiconductor devices that are stacked one on top of another. The amount of surface area on a carrier substrate that may be saved by stacking semiconductor devices is readily apparent-a stack of semiconductor devices consumes roughly the same amount of real estate on a carrier substrate as a single, horizontally oriented semiconductor device or semiconductor device package.
Due to the disparity in processes that are used to form different types of semiconductor devices (e.g., the number and order of various process steps), it has proven very difficult to actually incorporate different types of functionality into a single semiconductor device. Even in cases where semiconductor devices that carry out multiple functions can be fabricated, multi-chip modules that include semiconductor devices with differing functions (e.g., memory, processing capabilities, etc.) are often much more desirable since the separate semiconductor devices may be fabricated and assembled with one another much more quickly and cost effectively (e.g., lower production costs due to higher volumes and lower failure rates).
Multi-chip modules may also contain a number of semiconductor devices that perform the same function, effectively combining the functionality of all of the semiconductor devices thereof into a single package.
An example of a conventional, stacked multi-chip module includes a carrier substrate, a first, larger semiconductor device secured to the carrier substrate and a second, smaller semiconductor device positioned over and secured to the first semiconductor device. The second semiconductor device does not overlie bond pads of the first semiconductor device and, thus, the second semiconductor device does not cover bond wires that electrically connect bond pads of the first semiconductor device to corresponding contacts or terminals of the carrier substrate. Such a multi-chip module is disclosed and illustrated in U.S. Pat. No. 6,212,767, issued to Tandy on Apr. 10, 2001 (hereinafter “the '767 Patent”). As the sizes of the semiconductor devices of such a multi-chip module continue to decrease as they are positioned increasingly higher on the stack, the obtainable heights of such multi-chip modules become severely limited.
Another example of a conventional multi-chip module is described in U.S. Pat. No. 5,323,060, issued to Fogal et al. on Jun. 21, 1994 (hereinafter “the '060 Patent”). The multi-chip module of the '060 Patent includes a carrier substrate with semiconductor devices disposed thereon in a stacked arrangement. The individual semiconductor devices of each multi-chip module may be the same size or different sizes, with upper semiconductor devices being either smaller or larger than underlying semiconductor devices. Adjacent semiconductor devices of each of the multi-chip modules disclosed in the '060 Patent are secured to one another with an adhesive layer. The thickness of each adhesive layer exceeds the loop heights of bond wires protruding from a semiconductor device upon which that adhesive layer is to be positioned. Accordingly, the presence of each adhesive layer prevents the back side of an overlying, upper semiconductor device from contacting bond wires that protrude from an immediately underlying, lower semiconductor device of the multi-chip module. The adhesive layers of the multi-chip modules disclosed in the '060 Patent do not encapsulate or otherwise cover any portion of the bond wires that protrude from any of the lower semiconductor devices. The multi-chip modules of the '060 Patent may be undesirably thick due to the large vertical distance between each adjacent pair of semiconductor devices that ensures that the back side of each upper semiconductor device is electrically isolated from the bond wires protruding over the active surface of the next, lower semiconductor device, which may result in wasted adhesive and excessive stack height.
A similar but more compact multi-chip module is disclosed in U.S. Patent Re. 36,613, issued to Ball on Mar. 14, 2000 (hereinafter “the '613 Patent”). The multi-chip module of the '613 Patent includes many of the same features as those disclosed in the '060 Patent, including adhesive layers that space vertically adjacent semiconductor devices apart a greater distance than the loop heights of bond wires protruding from the lower of the adjacent dice. The use of thinner bond wires with low loop profile wire bonding techniques permits adjacent semiconductor devices of the multi-chip module disclosed in the '060 Patent to be positioned more closely to one another than adjacent semiconductor devices of the multi-chip modules disclosed in the '060 Patent. Nonetheless, additional space remains between the tops of the bond wires protruding from one semiconductor device and the back side of the next higher semiconductor device of such a stacked multi-chip module.
Preformed silicon spacers are typically used to separate stacked semiconductor devices a sufficient distance from one another so that the back side of an upper semiconductor device will not contact underlying bond wires or other discrete conductive elements protruding above an active surface of a next lower semiconductor device. The use of silicon, polymeric films, or other preformed spacers is somewhat undesirable from the standpoint that each time a preformed spacer is used, additional alignment and assembly steps are required. For example, a preformed spacer must be positioned on an active surface of a semiconductor device in such a manner that the bond pads thereof or discrete conductive elements extending thereover are exposed beyond an outer periphery of the spacer. Further, when silicon spacers are used, adhesive material must be applied to either the spacer or the semiconductor devices the spacer is to be positioned between. As is well understood by those in the art of semiconductor device fabrication, additional alignment and assembly steps may decrease product yields and consequently increase production costs.
The vertical distance that adjacent semiconductor devices of a stacked type multi-chip module are spaced apart from one another may be reduced by arranging the semiconductor devices such that upper semiconductor devices are not positioned over bond pads of immediately underlying semiconductor devices or the bond wires or other discrete conductive elements protruding from these bond pads. Thus, adjacent semiconductor devices may be vertically spaced apart from one another a distance that is about the same as or less than the loop heights of the bond wires that protrude above the active surface of the lower semiconductor device. U.S. Pat. No. 6,051,886, issued to Fogal et al. on Apr. 18, 2000 (hereinafter “the '886 Patent”) discloses such a multi-chip module. According to the '886 Patent, wire bonding is not conducted until all of the semiconductor devices of such a multi-chip module have been assembled with one another and with the underlying carrier substrate. The semiconductor devices of the multi-chip modules disclosed in the '886 Patent must have bond pads that are arranged on opposite peripheral edges. Semiconductor devices with bond pads positioned adjacent the entire peripheries thereof could not be used in the multi-chip modules of the '886 Patent. This is a particularly undesirable limitation due to the ever-increasing feature density of state-of-the-art semiconductor devices, which is often accompanied by a consequent need for an ever-increasing number of bond pads on semiconductor devices, as well as arrangement of bond pads over greater portions of the active surfaces of semiconductor devices.
In view of the foregoing, it appears that stacked assemblies in which an upper semiconductor device could be stacked over bond pads of an adjacent, lower semiconductor device to provide flexibility in bond pad number and placement would be useful, as would methods for forming such stacked assemblies. It also appears that methods and structures that reduce the number of different steps required in forming assemblies of stacked semiconductor devices would also be useful.